The present invention relates generally to design automation, and relates more particularly to the timing analysis of integrated circuit (IC) chips.
Manufacturing and environmental variations are unavoidable in integrated circuit (IC) chips. Delays and slews of signals propagated through logic gates and wires depend on these variations. Statistical timing is commonly used to analyze IC chips for timing violations in the range of these variations. Statistical timing assumes that manufacturing and environmental variations are random and therefore behave statistically. Applying this assumption, statistical timing analysis models chip timing statistically. It approximates timing accurately in the regions of highly probable values of variations while allowing higher error in the regions of less probable values of variations.
Conventionally, the delays of gates and wires in the chip are modeled in the linear canonical form of variational parameters, which is simple and efficient to propagate through the circuit. FIG. 1, for example, illustrates the conventional linear approach to modeling timing quantities in statistical timing. Specifically, FIG. 1 illustrates the delay D for an exemplary logic gate as a function of two sources of variation X and V. X and V in this case are linear, separable parameters. X and V may be set to any value within a range of values (i.e., X1-X2 and V1-V2, respectively). The delay is modeled in linear canonical form as D(V,X)=d0+dvΔV+dxΔX. The delay sensitivities dx and dv are computed by finite differencing, as illustrated. The delay sensitivities can also be computed by differentiating the delays of gates and wires with respect to variational variables. In some cases, the sensitivities of delays and slews can be assigned (asserted) assuming a known percentage of variability, without requiring explicit finite differencing or computing of derivatives. A process “corner” occurs where a boundary (i.e., highest or lowest possible) value of X meets a boundary value of Y. As illustrated, the linear canonical form is an exact model of the delay for all process corners when dealing with linear separable parameters.
Some variables, however, are not separable and thus do not interact linearly. For example, chips are designed to operate correctly in a range of supply voltages (Vdd); a circuit using a chip can set the supply voltage to any value in this range. At different supply voltages, the sensitivities of delays and slews to some parameters will be different, because the variations due to these parameters and the supply voltage are not separable. FIG. 2 illustrates the application of the linear approach illustrated in FIG. 1 to modeling timing quantities with non-separable parameters X and V. As illustrated, the linear form cannot model the delay exactly when the delay is a function of non-separable parameters.
Moreover, variables like supply voltage are not statistical, but deterministic. Chips must work at any voltage within the required range of voltage values. All voltage values in this range are equally important, even the lowest and highest (“corner”) values. The statistical approximation used by statistical timing analysis is not accurate enough to model variations of supply voltage or similar deterministic parameters. The statistical approximation cannot achieve sufficient accuracy near the corner values of the deterministic parameters, especially if some statistical parameters are not separable with the deterministic parameters.
Conventional statistical timing methodology therefore uses two timing runs at each voltage “corner” to account for these non-separable, non-statistical (deterministic) variations: a first timing run at a low supply voltage (V1) and a second timing run at a high supply voltage (V2). The use of multiple timing runs, however, is inefficient and inconvenient. For instance, timing closure will take longer and will require more computational resources. Additionally, a circuit optimized at one supply voltage will often fail at another supply voltage. This leads to multiple iterations in circuit design and optimization.
The deterministic variables requiring equally high accuracy of timing analysis across the entire range of variations including their corners are called “corner-based variables” due to the necessity of using corner analysis in their modeling.